The present invention generally relates to semiconductor memory devices and, more particularly, to Static Random Access Memory (SRAM) devices and to design structures for SRAM devices.
Referring to FIGS. 1A and B, in the known 6 transistor (6T) SRAM cell that is widely used in the industry today, read and write operations have different requirements for the access transistors (pass gates N3,N4). During the read operation, a pull-down transistor (e.g., N1) is fighting with the access transistor (e.g., N3) to pull a bitline BL voltage level down. Therefore, a strength of the access transistor N3 should be less than that of the pull-down transistor N1. During the write operation, the access transistor (e.g., N3) is fighting with a pull-up transistor P1 to pull the internal node down. Therefore, a strength of the access transistor N3 should be more than that of the pull up transistor P1. To satisfy requirements of both read and write operations, the access transistor N3 strength must be suitably between those of the pull-up and the pull-down transistors P1,N1. The same rationale applies to access transistor N4 and pull up and pull down transistors P2,N2. However, as the IC scaling continues to progress, it becomes increasingly challenging to control the variations in SRAM circuits. Thus, it is increasingly difficult to control access transistor strength to be suitably between those of the pull-up and the pull-down transistors. Various 6T and other SRAM devices, their methods of operation and process for their manufacture are described, for example, in U.S. Pat. No. 6,920,061, LOADLESS NMOS FOUR TRANSISTOR DYNAMIC DUAL VT SRAM CELL, filed Aug. 27, 2003, to Bhavnagarwala et al.; U.S. Pat. No. 7,217,978, SRAM MEMORIES AND MICROPROCESSORS HAVING LOGIC PORTIONS IMPLEMENTED IN HIGH-PERFORMANCE SILICON SUBSTRATES AND SRAM ARRAY PORTIONS HAVING FIELD EFFECT TRANSISTORS WITH LINKED BODIES AND METHOD FOR MAKING SAME, filed Jan. 19, 2005, to Joshi et al.; U.S. Pat. No. 7,295,458, EIGHT TRANSISTOR SRAM CELL WITH IMPROVED STABILITY REQUIRING ONLY ONE WORD LINE, filed Jan. 18, 2006, to Chan et al.; and U.S. Pat. No. 7,170,809, STABLE MEMORY WITH HIGH MOBILITY CELL DEVICES, filed May 13, 2005, to Joshi, which are all hereby incorporated in their entireties by reference.
Various techniques have been proposed in the prior art to address the difficult challenge. See for instance, in “2005 Symposium on VLSI Technology Digest of Technical Papers”, page 128-129, the paper titled “Stable SRAM Cell Design for the 32 nm Node and Beyond” which describes an 8-transistor SRAM cell to address the problem mentioned above. However, the 8-transistor SRAM design requires additional transistors, word-lines, and bit-lines, and therefore seems significantly to increase the area of the SRAM and to add process complexity.
Another example is U.S. Pat. No. 4,953,127 to Nagahashi et al. which describes a semiconductor memory having different read and write word line voltage levels. However, the choice of word line voltage levels is limited by device reliability and various other circuit and technology concerns. Therefore, its advantage seems to be limited.
Further, multiple conduction state field effect transistors (MCSFETs) are known. See, for example, U.S. Patent Application Publication No. 2006/0273393 to Chidambarrao et al., STRUCTURE AND METHOD OF MAKING FIELD EFFECT TRANSISTOR HAVING MULTIPLE CONDUCTION STATES, filed Jun. 7, 2005.
See also U.S. Pat. No. 7,123,529 to Hanson et al. U.S. Pat. No. 7,242,239 to Hanson et al. The '393 Publication, and the '529 and '239 patents are all hereby incorporated in their entireties by reference.
The multiple-conduction state FET (“MCSFET”) is similar to known FETs in that it has an essentially nonconductive state when a gate to source voltage applied to the MCSFET does not exceed a first threshold voltage. The MCSFET also has a fully conductive state when the gate to source voltage is above a second threshold voltage or “final threshold voltage” that enables the MCSFET to be fully conductive. The fully conductive state is defined as a level in which an inversion layer forms in the channel region as a result of the voltage applied between the gate and the source of the MCSFET.
However, unlike ordinary FETs, the first threshold voltage and the final threshold voltage have different values. When the gate to source voltage is between the first threshold voltage and the final threshold voltage the MCSFET has another conductive state in which the MCSFET is turned on, but conducts a relatively low amount of current. At that time, the MCSFET conducts a current having a magnitude which is ten or more times smaller than the current conducted when the MCSFET exceeds the final threshold voltage level. Here, when the gate to source voltage is at such level, the MCSFET is turned on, in that an inversion layer forms in a part of the channel region as a result of the voltage applied between the gate and the source of the MCSFET. The difference is that when the gate to source voltage is above the final threshold voltage and the MCSFET is in the second conductive state, the inversion layer of the MCSFET extends within a larger part of the channel region so as to turn on a larger part of the transistor. Thus, a predetermined part of the MCSFET smaller than the entire MCSFET becomes fully conductive when the gate-source voltage exceeds the first threshold voltage, and a remaining predetermined part of the MCSFET becomes fully conductive when the gate-source voltage exceeds the second or “final” threshold voltage level. In particular known embodiments, the MCSFET is fabricated in such way that the transistor has one threshold voltage for a first part of the width of the transistor channel, and has a higher threshold voltage for the remaining part of the transistor channel width. For example, the transistor can have a gate oxide that varies in thickness between the two parts of the transistor channel width and conditions in which threshold voltage implants are conducted in the two parts of the transistor channel can be varied in order to achieve the desired difference in threshold voltages.